With the development of a technique for reducing the power consumption of power conversion apparatuses, there are growing expectations for a technique for reducing the power consumption of a power device which plays a key role in the power conversion apparatus. For example, among various types of power devices, an insulated gate bipolar transistor (IGBT) has been generally used which can reduce the on-voltage using the conductivity modulation effect and whose operation is easily controlled by the control of a voltage-driven gate. The use of the IGBT makes it possible to ensure a high breakdown voltage and to significantly improve a switching speed even in a power device provided in a circuit area in which a large amount of current flows.
However, with an increase in the switching speed, EMI (Electro Magnetic Interference) noise problems have emerged. In particular, it is necessary to suppress the EMI noise to an allowable level when the IGBT is turned on. As a result, an increase in the switching speed is limited and it is difficult to sufficiently reduce switching loss. It is important to achieve a soft recovery free wheeling diode (FWD) which is combined with the IGBT in order to reduce the EMI noise.
In order to achieve the soft recovery FWD, it is necessary to reduce the carrier density of an anode to reduce a reverse recovery current during reverse recovery. In addition, it is necessary to increase the carrier density of a cathode in order to suppress the oscillation of a voltage-current waveform due to the depletion of the carriers. As a structure in which the carrier density of the anode is low and the carrier density of the cathode is high, the following structures have been known: an anode structure with low injection efficiency; a structure in which a Schottky diode is locally arranged; and a structure which controls a local lifetime to optimize a carrier distribution.
In recent years, as another structure in which the carrier density of the anode is low and the carrier density of the cathode is high, a structure has been proposed which forms a floating buried p layer on the cathode side, avalanches a pn diode on the cathode side when a high voltage is applied, and forcedly increases the carrier density of the cathode to achieve soft recovery (for example, see the following Patent Documents 1 and 2). The FWD according to the related art disclosed in the following Patent Documents 1 and 2 will be described with reference to FIG. 29. FIG. 29 is a cross-sectional view illustrating the structure of the FWD according to the related art.
As illustrated in FIG. 29, the FWD according to the related art includes an active region 100 and an edge termination structure portion (edge portion) 110 surrounding the active region 100, which are provided in an n− semiconductor substrate that will be an n− drift region 101. A p+ anode layer 102 is provided in a surface layer of the front surface of the n− semiconductor substrate in the active region 100. A field limiting ring (FLR) 108 is provided in a floating p-type region in the edge termination structure portion 110. An interlayer insulating film 109 covers the front surface of the n− semiconductor substrate in the edge termination structure portion 110. An anode electrode 103 is provided on the surface of the p+ anode layer 102 and has an end portion which extends onto the interlayer insulating film 109.
An n+ cathode layer 104 is provided in a surface layer of the rear surface of the n− semiconductor substrate so as to extend from the active region 100 to the edge termination structure portion 110. An n buffer layer 105 is provided between the n− drift region 101 and the n+ cathode layer 104 so as to extend from the active region 100 to the edge termination structure portion 110. A plurality of buried p layers 106 are provided in a surface layer of the n buffer layer 105 which is close to the n+ cathode layer 104 at predetermined intervals so as to extend from the active region 100 to the edge termination structure portion 110. The buried p layer 106 comes into contact with the n+ cathode layer 104. A cathode electrode 107 is provided on the entire rear surface of the n− semiconductor substrate.
As another FWD, a device has been proposed which includes a first electrode, a first layer of a first conductivity type that is provided on the first electrode, a second layer that is a second conductivity type different from the first conductivity type and is provided on the first layer, a third layer that is provided on the second layer, a second electrode that is provided on the third layer, and a fourth layer that is the second conductivity type and is provided between the second layer and the third layer. In the device, the third layer includes a first portion which is the second conductivity type and has an impurity concentration peak value greater than the impurity concentration peak value of the second layer and a second portion of the first conductivity type. The ratio of the area of the second portion to the total area of the first and second portions is equal to or greater than 90% and equal to or less than 95% (for example, see the following Patent Document 3).